PLL control circuits are widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Traditionally, the PLL circuit has been an analog block, including the basic components of a voltage control oscillator (VCO), phase and frequency detector (PFD), charge pump, low pass filter (LPF) and a feedback path. However, such analog PLL circuits include a number of capacitors which require a significantly large chip area. Additionally these circuits are very sensitive to power noise.
More recently, PLL circuit design has evolved to a greater use of digital control. The first generation digital PLL uses one external high frequency clock to sample the reference clock, then generates the output clock by dividing or multiplying a certain number according to requirement. The frequency of an external clock having accuracy required by such PLL circuit is limited with respect to its capability for applying a sampling rate that can accommodate high frequency reference clock signals. As this design can only be used in low frequency applications, a hybridization of analog and digital elements has been pursued. With such approach, chip area has not been significantly reduced, while performance is markedly decreased.
In one conventional PLL control system, to trace the phase of a reference clock, the cycle time of a feedback clock is adjusted based on (1) whether the feedback clock leads or lags the reference clock, and (2) the absolute value of skew between the two clocks. In a conventional PLL control system, the feedback clock needs a relatively long time to capture the phase of the reference clock. One problem is that the speed difference between the feedback clock and the reference clock is not considered, and therefore the actual feedback clock speed cannot be adjusted properly. This approach can result in skew oscillation such that the jitter is too large (e.g., cannot be reduced to a minimum or sufficiently small value). Moreover, this approach also requires a longer time for PLL to reach lock status (i.e., to get to a lock status from an unlock status).
A need exists for an improved PLL control system. Performance capabilities, such as high DCO frequency range, long term jitter control, low power consumption, low lock time, are highly desirable. Such a digital PLL circuit should encompass a small chip area and exemplify good performance.
Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.